1. Field of Invention
The present invention relates to an ESD protection circuit. More particularly, the present invention relates to a gate-coupled substrate-triggered ESD protection circuit in which a layout area therefor is significantly decreased.
2. Description of Related Art
With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron CMOS technologies. All of these processes make the related CMOS IC products to become more susceptible to electrostatic discharge (ESD) damage. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits of the IC against ESD damage. It is generally desired that the ESD robustness for commercial IC products be higher than 2 kV in human-body-model (HBM) ESD stress. To sustain ESD overstress, devices with large dimensions need to be designed into the on-chip ESD protection circuit, and require a large total layout area on the silicon substrate. Typically, an NMOS in an I/O ESD protection circuit has a total channel width that is greater than 300 μm. With such large device dimensions, the NMOS is often realized with multiple fingers in the layout. However, under an ESD stress, the multiple fingers of ESD protection NMOS do not uniformly turn on to bypass the ESD current. Only a portion of the fingers of the NMOS may be turned on, and consequently leading to damage from the ESD pulse. In this case, although the ESD protection NMOS has a very large device dimension, the ESD protection level is low. In order to improve the turn-on uniformity, a gate-driven design has been used to increase the ESD protection level of the large-device-dimension ESD protection NMOS. However, it has been found that the ESD protection level of the gate-driven NMOS decreases dramatically when the gate voltage is somewhat increased. The gate-driven design pulls ESD current flowing through the channel surface of the NMOS rather than the bulk. The NMOS is thus more easily burnt-out by the ESD energy. Please refer to FIG. 1, which shows a schematic circuit diagram of prior art ESD protection design 100 using a substrate-triggered technique. As shown in FIG. 1, the ESD protection circuit design 100 includes an NMOS 102, an internal circuit 104, a pad 106, a substrate-biasing circuit 108, and a conductor for electrically connecting the internal circuit 104 with the pad 106. The NMOS 102 further includes a source 112, a drain 114 electrically connected to the pad 106, a gate 116, and a substrate 118 biased by the substrate-biasing circuit 108. When a positive ESD voltage zaps the pad 106, the bulk (substrate) of the ESD protection NMOS 102 is biased at some voltage level generated by the substrate-biasing circuit 108. With the substrate-biasing voltage, parasitic lateral n-p-n bipolar junction transistor (BJT) 120 effects in the NMOS 102 are triggered on to discharge the ESD current. In this substrate-triggered technique, the ESD current flowing through the NMOS 102 is far from the channel surface.
The substrate-triggered effect turns on a parasitic lateral n-p-n BJT 120 of the NMOS 102 structure to pull the current to flow through the bulk of the NMOS 102, which is far from the surface channel of the NMOS, and so avoids the drain LDD edge structure. The bulk of the NMOS 102 has a larger volume to dissipate ESD-generated heat. The substrate-triggered NMOS 102 can thus sustain a much higher ESD level within the same silicon area. The substrate-triggered technique has consequently become more important in sub-quarter-micron CMOS processes for effective on-chip substrate-triggered ESD protection.
Another ESD protection design 100 using a substrate-triggered technique is proposed in the U.S. Pat. No. 6,465,768, entitled “MOS STRUCTURE WITH IMPROVED SUBSTRATE-TRIGGERED EFFECT FOR ON-CHIP ESD PROTECTION”, assigned to Ker et al., which is owned by the same assignee as the present application. Please refer to FIG. 2, which is a schematic circuit diagram of an output ESD protection circuit 200. The output ESD protection circuit 200 is realized by the substrate-triggered technique with the PMOS and NMOS device structure. As shown in FIG. 2, when a positive-to-VSS ESD zapping event occurs on the output pad 210, the VSS power terminal is grounded and the VDD power terminal is floated. The sharply-rising ESD voltage pulse is connected through a capacitor 202 to a gate 206 of NMOS 204. This connected voltage is maintained on the gate 206 of the NMOS 204 for a longer period of time by a resistor 208.
With a connected voltage greater than the threshold voltage (VTH) of the NMOS 204, the NMOS 204 is turned on and conducts some of the ESD current from the pad 210 through the ESD protection NMOS 212. With a trigger current generated from the NMOS 204, the ESD protection NMOS 212 is turned on more quickly to discharge the ESD current from the pad 210 to the VSS power terminal. The substrate-triggered current generated from the NMOS 204 triggers on the parasitic lateral n-p-n BJT 214 of the ESD protection NMOS 212 to pull the current to flow through the substrate (bulk) of the ESD protection NMOS 212, which is far from the surface channel of the ESD protection NMOS 212. The bulk of the ESD protection NMOS 212 has a larger volume to dissipate ESD-generated heat, and therefore the substrate-triggered ESD protection NMOS 212 can sustain a much higher ESD protection level.
With a negative-to-VDD ESD zapping on the output pad 210, the VDD power terminal is grounded and the VSS power terminal is floated. The sharply-falling negative ESD voltage pulse is connected through the capacitor 222 to the gate 226 of the PMOS 224. This connected voltage is maintained on the gate 226 of the PMOS 224 for a longer period of time by resistor 228. With a connected negative gate voltage, the PMOS 224 is turned on and conducts some negative ESD current from the pad 210 through the ESD protection PMOS 232. With a trigger current generated from the PMOS 224, the ESD protection PMOS 232 is turned on more quickly to discharge the negative ESD current from the pad 210 to the VDD power terminal. The substrate-triggered current generated from the PMOS 224 triggers on the parasitic lateral p-n-p BJT 234 of the ESD protection PMOS 232 to pull the current to flow through the N-type well (bulk) of the ESD protection PMOS 232, which is far from the surface channel of the ESD protection PMOS 232. The bulk of the ESD protection PMOS 232 has a larger volume to dissipate ESD-generated heat, and therefore the substrate-triggered ESD protection PMOS 232 can sustain a much higher ESD protection level.
However, in these proposed ESD protection design using a substrate-triggered technique, a RC time constant will consume a larger of layout area. The power clamp layout of the ESD protection design will also consume a large of layout area.